set_property SRC_FILE_INFO {cfile:D:/programs/FPGA/fpga-learning/uart_packet/uart_packet.srcs/constrs_1/new/top_uart_packet.xdc rfile:../../../uart_packet.srcs/constrs_1/new/top_uart_packet.xdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE5 [get_ports sys_clk_p]
set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF5 [get_ports sys_clk_n]
set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports sys_rst_n]
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports uart_txd]
